![]() ![]() Shared 元 cache which includes the processor graphics ( LGA 1155).32 KB data + 32 KB instruction L1 cache and 256 KB L2 cache per core.Intel demonstrated a Sandy Bridge processor with A1 stepping at 2 GHz during the Intel Developer Forum in September 2009. Sandy Bridge is manufactured in the 32 nm process and has a soldered contact with the die and IHS (Integrated Heat Spreader), while Intel's subsequent generation Ivy Bridge uses a 22 nm die shrink and a TIM (Thermal Interface Material) between the die and the IHS. Intel demonstrated a Sandy Bridge processor in 2009, and released first products based on the architecture in January 2011 under the Core brand. The Sandy Bridge microarchitecture is the successor to Nehalem and Westmere microarchitecture. Sandy Bridge is the codename for Intel's 32 nm microarchitecture used in the second generation of the Intel Core processors ( Core i7, i5, i3). Bottom view of a Sandy Bridge i7-2600k Top of a Sandy Bridge i5 ![]()
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